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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd720114 ecousb tm series usb 2.0 hub controller document no. s17462ej2v0ds00 (2nd edition) date published may 2005 ns cp (k) printed in japan data sheet 2005 the pd720114 is a usb 2.0 hub device that co mplies with the universal serial bus (usb) specification revision 2.0 and works up to 480 mbps. usb 2.0 compliant transceiver s are integrated for upstream and all downstream ports. the pd720114 works backward compatible either when any one of the downstream ports is connected to a usb 1.1 compliant device, or when the upstream port is connected to a usb 1.1 compliant host. detailed function descriptions are provided in the following user?s manual. be sure to read the manual before designing. pd720114 user?s manual: s17463e features ? compliant with universal serial bus specif ication revision 2.0 (dat a rate 1.5/12/480 mbps) ? high-speed or full-speed packet prot ocol sequencer for endpoint 0/1 ? 4 (max.) downstream facing ports ? all downstream facing ports can handle high-speed ( 480 mbps), full-speed (12 m bps), and low-speed (1.5 mbps) transaction. ? supports split transaction to handle full-speed and lo w-speed transaction on downstream facing ports when hub controller is working in high-speed mode. ? one transaction translator per hub and supports four non-periodic buffers ? supports self-power ed and bus-powered mode ? supports individual or global over-current detection and individual or ganged power control ? supports downstream port status with led ? supports non-removable devices by i/o pin configuration ? support energy star for pc peripheral system ? on chip rpu, rpd resistors and regulator (for core logic) ? low power consumption ? use 30 mhz x?tal ? 3.3 v power supply
data sheet s17462ej2v0ds 2 pd720114 ordering information part number package remark pd720114ga-9eu-a 48-pin plastic tqfp (fine pitch) (7 7) lead-free product block diagram upstream facing port up_phy downstream facing port #1 serdes sie_2h cdr apll osb upc all_tt f_tim ep1 ep0 dp(1)_phy downstream facing port #2 dp(2)_phy downstream facing port #3 dp(3)_phy downstream facing port #4 dp(4)_phy dpc fs_rep to host/hub downstream facing port x1/x2 ppb(4:1) csb(4:1) to hub/function upstream facing port to hub/function upstream facing port to hub/function upstream facing port to hub/function upstream facing port cdr 2.5v reg
data sheet s17462ej2v0ds 3 pd720114 apll : generates all clocks of hub. all_tt : translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. all_tt buffers the data transfer from either upstream or downstream direction. for out transaction, all_tt buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. for in transaction, all_tt buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/ low-speed to high-speed. cdr : data & clock recovery circuit dpc : downstream port controller handles port reset, enable, disable, suspend and resume dp(n)_phy : downstream transceiver supports hi gh-speed (480 mbps), full- speed (12 mbps), and low-speed (1.5 mbps) transaction ep0 : endpoint 0 controller ep1 : endpoint 1 controller f_tim (frame timer) : manages hub?s synchronization by using micro-sof which is received at upstream port, and generates sof packet when full/low-speed device is attached to downstream facing port. fs_rep : full/low-speed repeater is enabled when the pd720114 are worked at full-speed mode osb : oscillator block 2.5v reg : on chip 2.5v regulator serdes : serializer and deserializer sie_2h : serial interface engine (sie) c ontrols usb2.0 and 1.1 protocol sequencer. up_phy : upstream transceiver supports high -speed (480 mbps), full-speed (12 mbps) transaction upc : upstream port controller handles suspend and resume
data sheet s17462ej2v0ds 4 pd720114 pin configuration (top view) ? 48-pin plastic tqfp (fine pitch) (7 7) pd720114ga-9eu-a 44 bus_b test rref av ss(r) av dd av ss av dd v dd33 dmu dpu v ss v dd25 v ss dp4 dm4 v dd25 dp3 dm3 v dd33 dp2 dm2 v ss dp1 dm1 v dd25out v ssreg led4 led3 led2 led1 green amber v dd33 x1 x2 v dd25 v dd33reg vbusm csb1 ppb1 csb2 ppb2 v ss csb3 ppb3 csb4 ppb4 sysrstb 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 16 14 15 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 45 46 47 48
data sheet s17462ej2v0ds 5 pd720114 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v dd25out 13 bus_b 25 dm1 37 sysrstb 2 v ssreg 14 test 26 dp1 38 ppb4 3 led4 15 rref 27 v ss 39 csb4 4 led3 26 av ss (r) 28 dm2 40 ppb3 5 led2 17 av dd 29 dp2 41 csb3 6 led1 18 av ss 30 v dd33 42 v ss 7 green 19 av dd 31 dm3 43 ppb2 8 amber 20 v dd33 32 dp3 44 csb2 9 v dd33 21 dmu 33 v dd25 45 ppb1 10 x1 22 dpu 34 dm4 46 csb1 11 x2 23 v ss 35 dp4 47 vbusm 12 v dd25 24 v dd25 36 v ss 48 v dd33reg remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 2.43 k ? .
data sheet s17462ej2v0ds 6 pd720114 1. pin information pin name i/o buffer type active level function x1 i 2.5 v input 30mhz crystal oscillator in x2 o 2.5 v output 30mhz crystal oscillator out sysrstb i 3.3 v schmitt input low asynchronous chip hardware reset dp(4:1) i/o usb d + signal i/o usb?s downstream facing port d + signal dm(4:1) i/o usb d ? signal i/o usb?s downstream facing port d ? signal dpu i/o usb d + signal i/o usb?s upstream facing port d + signal dmu i/o usb d ? signal i/o usb?s upstream facing port d ? signal bus_b i 3.3 v schmitt input power mode select rref a (o) analog refer ence resistor connection csb1 i 5 v tolerant schmitt input lo w port?s over-current status input. csb(4:2) i 3.3 v schmitt input low port?s over-current status input ppb(4:1) i/o 3.3 v output / input low port?s power supply control output or hub configuration input vbusm i 5 v tolerant schmitt input upstream v bus monitor amber i/o 3.3v output / input amber colored led control output or port indicator select green o 3.3v output green colored led control output or port indicator select led(4:1) i/o 3.3v output / input low led indicator output show downstream port status or removable/non-removable select test i 3.3 v schmitt input test signal v dd25out on chip 2.5 v regulator output, it must have a 4.7 f (or greater) capacitor to v ssreg v dd33 3.3 v v dd v dd33reg 3.3 v v dd for on chip 2.5v regulator input, it must have a 4.7 f ( or greater) capacitor to v ssreg v dd25 2.5 v v dd av dd 2.5 v v dd for analog circuit v ss v ss v ssreg on chip 2.5 v regulator v ss av ss v ss for analog circuit av ss (r) v ss for reference resistor, connect to av ss . remark ?5 v tolerant? means that the buffer is 3 v buffer with 5 v tolerant circuit.
data sheet s17462ej2v0ds 7 pd720114 2. electrical specifications 2.1 buffer list ? 2.5 v oscillator interface x1, x2 ? 5 v tolerant schmitt input buffer csb1, vbusm ? 3.3 v schmitt input buffer csb(4:2),bus_b, sysrstb, test ? 3.3 v i ol = 12 ma output buffer green ? 3.3 v input and 3.3 v i ol = 3 ma output buffer ppb(4:1), led(4:1) ? 3.3 v input and i ol = 12 ma output buffer amber ? usb2.0 interface dpu, dmu, dp(4:1), dm(4:1), rref above, ?5 v? refers to a 3 v input bu ffer that is 5 v tolerant (has 5 v ma ximum input voltage). therefore, it is possible to have a 5 v connection for an external bus.
data sheet s17462ej2v0ds 8 pd720114 2.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd33 indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance values for dc current to prevent damage or reduced reliability when current flows out of or into an output pin. operating temperature t a indicates the ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. terms used in recommended operating range parameter symbol meaning power supply voltage v dd33 indicates the voltage range for normal logic operations to occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, applied to the input pins of the device, which indicates the high level state for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, applied to the input pins of the device, which indicates the low level state for normal operation of the input buffer. * if a voltage that is equal to or less than the ?max.? value is applied, the input voltage is guaranteed as low level voltage. hysteresis voltage v h indicates the differential between the positive trigger voltage and the negative trigger voltage. input rise time t ri indicates allowable input rise time to input signal transition time from 0.1 v dd to 0.9 v dd . input fall time t fi indicates allowable input fall time to input signal transition time from 0.9 v dd to 0.1 v dd .
data sheet s17462ej2v0ds 9 pd720114 terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows into a 3-state output pin when it is in a high- impedance state and a voltage is applied to the pin. output short circuit current i os indicates the current that flows from an output pin when it is shorted to gnd pins. input leakage current i i indicates the current that flows into an input pin when a voltage is applied to the pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that can flow out of an output pin in the high-level state without reducing the output voltage below the specified v oh . (a negative current indicates current flowing out of the pin.) 2.3 electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd33 ? 0.5 to + 4.6 v input/output voltage v i /v o 3.3 v input/output voltage 3.0 v v dd33 3.6 v v i /v o < v dd33 + 1.0 v ? 0.5 to + 4.6 v 5 v input/out voltage 3.0 v v dd33 3.6 v v i /v o < v dd33 + 3.0 v ? 0.5 to + 6.6 v output current i o i ol = 3 ma i ol = 6 ma i ol = 12 ma 10 20 40 ma ma ma operating temperature t a 0 to + 70 c storage temperature t stg ? 65 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc char acteristics and ac characteristics represent the quality assurance range during normal operation.
data sheet s17462ej2v0ds 10 pd720114 recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd33 3.3 v for v dd33 pins 3.14 3.30 3.46 v high-level input voltage v ih 3.3 v high-level input voltage 2.0 v dd33 v 5.0 v high-level input voltage 2.0 5.5 v low-level input voltage v il 3.3 v low-level input voltage 0 0.8 v 5.0 v low-level input voltage 0 0.8 v hysteresis voltage v h 5 v hysteresis voltage 0.3 1.5 v 3.3 v hysteresis voltage 0.2 1.0 v input rise time for sysrstb t rst 10 ms input rise time t ri normal buffer 0 200 ns schmitt buffer 0 10 ms input fall time t fi normal buffer 0 200 ns schmitt buffer 0 10 ms
data sheet s17462ej2v0ds 11 pd720114 dc characteristics parameter symbol condition min. max. unit off-state output leakage current i oz v o = v dd33, v dd25 or v ss 10 a output short circuit current i os note ? 250 ma low-level output current i ol 3.3 v low-level output current v ol = 0.4 v 3 ma 3.3 v low-level output current v ol = 0.4 v 6 ma 5.0 v low-level output current v ol = 0.4 v 12 ma high-level output current i oh 3.3 v high-level output current v oh = 2.4 v ? 3 ma 3.3 v high-level output current v oh = 2.4 v ? 6 ma 5.0 v high-level output current v oh = 2.4 v ? 2 ma input leakage current i i 3.3 v buffer v i = v dd or v ss 10 a 5.0 v buffer v i = v dd or v ss 10 a note the output short circuit time is measured at one second or less and is tested with only one pin on the lsi.
data sheet s17462ej2v0ds 12 pd720114 usb interface block parameter symbol conditions min max unit output pin impedance z hsdrv includes r s resistor 40.5 49.5 ? termination voltage for upstream facing port pullup (full-speed) v term 3.0 3.6 v input levels for low-/full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 v low-level input voltage v il 0.8 v differential input sensitivity v di ? (d + ) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for low-/full-speed: high-level output voltage v oh r l of 14.25 k ? to gnd 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch det ection threshold (differential signal) v hssq 100 150 mv high-speed disconnect detection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling levels see figure 2-4. output levels for high-speed: high-speed idle state v hsoi ? 10.0 + 10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10.0 + 10 mv chirp j level (different signal) v chirpj 700 1100 mv chirp k level (different signal) v chirpk ? 900 ? 500 mv
data sheet s17462ej2v0ds 13 pd720114 figure 2-1. differential input sensitivity range for low-/full-speed 4.6 -1.0 input voltage range (volts) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 2-2. full-speed buffer v oh /i oh characteristics for high-speed capable transceiver max. min. ? 80 ? 60 ? 40 ? 20 0 v dd ? 0.3 v out (v) i out (ma) v dd ? 2.3 v dd ? 3.3 v dd ? 0.8 v dd v dd ? 1.3 v dd ? 1.8 v dd ? 2.8 figure 2-3. full-speed buffer v ol /i ol characteristics for high-speed capable transceiver max. min. 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
data sheet s17462ej2v0ds 14 pd720114 figure 2-4. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 2-5. receiver measurement fixtures v bus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s17462ej2v0ds 15 pd720114 power consumption parameter symbol condition typ. unit power consumption p w-0 the power consumption under the state without suspend. all the ports do not connect to any function. hub controller is operating at full-speed mode. hub controller is operating at high-speed mode. 31 86 ma ma p w-2 the power consumption under the state without suspend. the number of active ports is 2. hub controller is operating at full-speed mode. hub controller is operating at high-speed mode. 36 120 ma ma p w-3 the power consumption under the state without suspend. the number of active ports is 3. hub controller is operating at full-speed mode. hub controller is operating at high-speed mode. 38 134 ma ma p w-4 the power consumption under the state without suspend. the number of active ports is 4. hub controller is operating at full-speed mode. hub controller is operating at high-speed mode. 41 149 ma ma p w_s the power consumption under suspend state. 220 a remark the power consumption depends on the number of ports available and actively operating. ports available but inactive or unplugged do not add to the power consumption. if the pd720114 is locally powered and the upstream facing port is unplugged, pd720114 goes into suspend state and downstream facing port vbus goes down.
data sheet s17462ej2v0ds 16 pd720114 system clock ratings parameter symbol condition min. typ. max. unit clock frequency f clk x?tal ? 500 ppm 30 + 500 ppm mhz clock duty cycle t duty 40 50 60 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of x?tal is including initia l frequency accuracy, the spread of x?tal capacitor loading, supply voltage, temp erature, and aging, etc. ac characteristics (v dd = 3.14 to 3.46 v, t a = 0 to + 70 c) system reset timing parameter symbol conditions min. max. unit reset active time (figure 2-6) t rst 5 s figure 2-6. system reset timing sysrstb t rst
data sheet s17462ej2v0ds 17 pd720114 over-current response timing parameter symbol condition min. typ. max. unit over-current response time from csb low to ppb high (figure 2-7) t oc 4 5 ms figure 2-7. over-current response timing c sb(4:1) p pb(4:1) t oc figure 2-8. csb/ppb timing bus reset port power supply on device connection inrush current output cut-off overcurrent generation hub power supply up port d+ line ppb pin output csb pin input csb pin opration region bus power: up port connection self power: power supply on csb active period csb detection delay time 4ms 4ms 4ms 4ms remark the active period of the csb pin is in effect only when the ppb pin is on. there is a delay time of approxim ately 4 ms duration at the csb pin.
data sheet s17462ej2v0ds 18 pd720114 usb interface block (1/4) parameter symbol conditions min. max. unit low-speed electrical characteristics rise time (10% to 90%) t lr c l = 200 pf to 600 pf 75 300 ns fall time (90% to 10%) t lf c l = 200 pf to 600 pf 75 300 ns differential rise and fall time matching t lrfm (t lr /t lf ) note 80 125 % low-speed data rate t ldraths average bit rate 1.49925 1.50075 mbps downstream facing port source jitter total (including frequency to lerance) (figure 2-13): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 + 25 + 14 ns ns downstream facing port differential receiver jitter total (including frequency tolerance) (figure 2-15): to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 + 152 + 200 ns ns source se0 interval of eop (figure 2-14) t leopt 1.25 1.5 s receiver se0 interval of eop (figure 2-14) t leopr 670 ns width of se0 interval during differential transition t lst 210 ns hub differential data delay (figure 2-11) t lhdd 300 ns hub differential driver jitter (including cable) (figure 2-11): downstream facing port to next transition for paired transitions upstream facing port to next transition for paired transitions t ldhj1 t ldhj2 t luhj1 t luhj2 ? 45 ? 15 ? 45 ? 45 + 45 + 15 + 45 + 45 ns ns ns ns data bit width distortion after sop (figure 2-11) t lsop ? 60 + 60 ns hub eop delay relative to t hdd (figure 2-12) t leopd 0 200 ns hub eop output width skew (figure 2-12) t lhesk ? 300 + 300 ns full-speed electrical characteristics rise time (10% to 90%) t fr c l = 50 pf, r s = 36 ? 4 20 ns fall time (90% to 10%) t ff c l = 50 pf, r s = 36 ? 4 20 ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms note excluding the first transit ion from the idle state.
data sheet s17462ej2v0ds 19 pd720114 (2/4) parameter symbol conditions min. max. unit full-speed electrical characteristics (continued) consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance) (figure 2-13): to next transition for paired transitions t dj1 t dj2 note ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition (figure 2-14) t fdeop ? 2 + 5 ns receiver jitter (figure 2-15): to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop (figure 2-14) t feopt 160 175 ns receiver se0 interval of eop (figure 2-14) t feopr 82 ns width of se0 interval during differential transition t fst 14 ns hub differential data delay (figure 2-11) (with cable) (without cable) t hdd1 t hdd2 70 44 ns ns hub differential driver jitter (including cable) (figure 2-11): to next transition for paired transitions t hdj1 t hdj2 ? 3 ? 1 + 3 + 1 ns ns data bit width distortion after sop (figure 2-11) t fsop ? 5 + 5 ns hub eop delay relative to t hdd (figure 2-12) t feopd 0 15 ns hub eop output width skew (figure 2-12) t fhesk ? 15 + 15 ns high-speed electrical characteristics rise time (10% to 90%) t hsr 500 ps fall time (90% to 10%) t hsf 500 ps driver waveform see figure 2-9. high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high- speed bit times data source jitter see figure 2-9. receiver jitter tolerance see figure 2-4. hub data delay (without cable) t hshdd 36 high- speed + 4 ns bit times hub data jitter see figure 2-4, figure 2-9. hub delay variation range t hshdv 5 high- speed bit times note excluding the first transit ion from the idle state.
data sheet s17462ej2v0ds 20 pd720114 (3/4) parameter symbol conditions min. max. unit hub event timings time to detect a downstream facing port connect event (figure 2-17): awake hub suspended hub t dcnn 2.5 2.5 2000 12000 s s time to detect a disconnect event at a hub?s downstream facing port (figure 2-16) t ddis 2.0 2.5 s duration of driving resume to a downstream port (only from a controlling hub) t drsmdn 20 ms time from detecting downstream resume to rebroadcast t ursm 1.0 ms duration of driving reset to a downstream facing port (figure 2-18) t drst only for a setportfeature (port_reset) request 10 20 ms time to detect a long k from upstream t urlk 2.5 100 s time to detect a long se0 from upstream t urlse0 2.5 10000 s duration of repeating se0 upstream (for low-/full-speed repeater) t urpse0 23 fs bit times inter-packet delay (for high-speed) of packets traveling in same direction t hsipdsd 88 bit times inter-packet delay (for high-speed) of packets traveling in opposite direction t hsipdod 8 bit times inter-packet delay for device/root hub response with detac hable cable for high- speed t hsrspipd1 192 bit times time of which a chirp j or chirp k must be continuously detected (filtered) by hub or device during reset handshake t filt 2.5 s time after end of device chirp k by which hub must start driving first chirp k in the hub?s chirp sequence t wtdch 100 s time for which each individual chirp j or chirp k in the chirp sequence is driven downstream by hub during reset t dchbit 40 60 s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 s time from internal power good to device pulling d + beyond v ihz (figure 2-18) t sigatt 100 ms debounce interval provided by usb system software after attach (figure 2-18) t attdb 100 ms maximum duration of suspend averaging interval t susavgi 1 s period of idle bus before device can initiate resume t wtrsm 5 ms duration of driving resume upstream t drsmup 1 15 ms
data sheet s17462ej2v0ds 21 pd720114 (4/4) parameter symbol conditions min. max. unit hub event timings (continued) resume recovery time t rsmrcy remote-wakeup is enabled 10 ms time to detect a reset from upstream for non high-speed capable devices t detrst 2.5 10000 s reset recovery time (figure 2-18) t rstrcy 10 ms inter-packet delay for full-speed t ipd 2 bit times inter-packet delay for device response with detachable cable for full-speed t rspipd1 6.5 bit times setaddress() completion time t dsetaddr 50 ms time to complete standard request with no data t drqcmpltnd 50 ms time to deliver first and subsequent (except last) data for standard request t dretdata1 500 ms time to deliver last data for standard request t dretdatan 50 ms time for which a suspended hub will see a continuous se0 on upstream before beginning the high-speed detection handshake t filtse0 2.5 s time a hub operating in non-suspended full-speed will wait after start of se0 on upstream before beginning the high-speed detection handshake t wtrstfs 2.5 3000 ms time a hub operating in high-speed will wait after start of se0 on upstream before reverting to full-speed t wtrev 3.0 3.125 ms time a hub will wait after reverting to full- speed before sampling the bus state on upstream and beginning the high-speed will wait after start of se0 on upstream before reverting to full-speed t wtrsths 100 875 ms minimum duration of a chirp k on upstream from a hub within the reset protocol t uch 1.0 ms time after start of se0 on upstream by which a hub will complete its chirp k within the reset protocol t uchend 7.0 ms time between detection of downstream chip and entering high-speed state t wths 500 s time after end of upstream chirp at which hub reverts to full-speed default state if no downstream chirp is detected t wtfs 1.0 2.5 ms
data sheet s17462ej2v0ds 22 pd720114 figure 2-9. transmit waveform for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 2-10. transmitter measurement fixtures v bus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s17462ej2v0ds 23 pd720114 timing diagram figure 2-11. hub differential delay, differential jitter, and sop distortion c. upstream hub delay with or without cable d. measurement points 50% point of initial swing 50% point of initial swing upstream end of cable upstream port of hub downstream port of hub downstream port of hub downstream port of hub upstream port or end of cable a. downstream hub delay with cable b. downstream hub delay without cable hub delay downstream t hdd1 hub delay upstream t hdd1 t hdd2 crossover point crossover point crossover point v ss hub differential jitter: t hdj1 = t hddx (j) ? t hddx (k) or t hddx (k) ? t hddx (j) consecutive transitions t hdj2 = t hddx (j) ? t hddx (j) or t hddx (k) ? t hddx (k) paired transitions bit after sop width distortion (same as data jitter for sop and next j transition): t fsop = t hddx (next j) ? t hddx (sop) low-speed timings are determined in the same way for: t lhdd , t ldhj1 , t ldjh2 , t luhj1 , t lujh2 , and t lsop host or hub hub function upstream end of cable upstream port downstream port downstream signaling upstream signaling plug receptacle hub delay downstream t hdd2 v ss v ss v ss v ss v ss
data sheet s17462ej2v0ds 24 pd720114 figure 2-12. hub eop delay and eop skew t eop- t eop+ t eop- t eop+ t eop- t eop+ c. upstream eop delay with or without cable upstream end of cable upstream port of hub downstream port of hub d ownstream port of hub downstream port of hub upstream port or end of cable a. downstream eop delay with cable b. downstream eop delay without cable v ss v ss v ss v ss v ss v ss 50% point of initial swing crossover point extended crossover point extended crossover point extended eop delay: t feopd = t eopy ? t hddx (t eopy means that this equation applies to t eop- and t eop+ ) eop skew: t fhesk = t eop+ ? t eop- low-speed timings are determined in the same way for: t leopd and t lhesk
data sheet s17462ej2v0ds 25 pd720114 figure 2-13. usb differential data jitter for low-/full-speed t period differential data lines crossover points consecutive transitions n t period + t xdj1 paired transitions n t period + t xdj2 figure 2-14. usb differential-to-eop transition skew and eop width for low-/full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt receiver eop width: t feopr t leopt t leopr diff. data-to- se0 skew n t period + t xdeop figure 2-15. usb receiver jitter tolerance for low-/full-speed differential data lines t period t xjr t xjr1 t xjr2 consecutive transitions n t period + t xjr1 paired transitions n t period + t xjr2
data sheet s17462ej2v0ds 26 pd720114 figure 2-16. low-/full-speed disconnect detection d ? /d + d + /d ? v ihz (min) v il v ss device disconnected disconnect detected t ddis figure 2-17. full-/high-speed device connect detection v ih v ss device connected connect detected d ? d + t dcnn figure 2-18. power-on and connection events timing t sigatt ? t1 t rstrcy d + or d ? hub port power ok attatch detected reset recovery time usb system software reads device speed 4.01 v v bus v ih (min) v ih hub port power-on t attdb t 2susp t drst
data sheet s17462ej2v0ds 27 pd720114 3. package drawing s s n j detail of lead end r k m l p i s q g f m h 4 8-pin plastic tqfp (fine pitch) (7x7) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 9.0 0.2 7.0 0.2 0.5 (t.p.) 0.75 j 9.0 0.2 k c 7.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 0.75 n p q 0.10 1.0 0.1 0.1 0.05 s48ga-50-9eu- 2 s 1.27 max. h 0.22 + 0.05 ? 0.04 m 0.145 + 0.055 ? 0.045 r3 + 7 ? 3 36 37 24 48 1 13 12 25 cd a b
data sheet s17462ej2v0ds 28 pd720114 4. recommended soldering conditions the pd720114 should be soldered and mounted un der the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) pd720114ga-9eu-a: 48-pin plastic tqfp (fine pitch) (7 7) soldering method solder ing conditions symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less exposure limit: 3 days note (after that, prebake at 125c for 10 hours) flux: rosin flux with low chlorine (0.2 wt% or below) recommended. ir60-103-3 partial heating pin temperature: 300c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period.
data sheet s17462ej2v0ds 29 pd720114 [memo]
data sheet s17462ej2v0ds 30 pd720114 [memo]
data sheet s17462ej2v0ds 31 pd720114 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd720114 ecousb is a trademark of nec electronics corporation. the information in this document is current as of may 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?

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